Embodiments of the present invention relate to processors, and more particularly to communication of data transactions throughout a system.
As processors evolve, greater amounts of instructions are performed within a given time and consequently greater amounts of data are passed into and out of a processor. Modern architectures are often formed using multiple cores in a single processor socket. After processing data in a given core, oftentimes the data is sent to other locations of a system as part of a data transaction. Different types of data transactions exist. In a given system protocol, some transactions have a more pressing time constraint than other transactions.
In some system implementations, a simple first-in-first-out (FIFO) buffer is used to store outgoing data transactions which are thus sent from the FIFO buffer in an in-order manner. However, such ordering prevents data transactions of a higher priority from passing transactions of a lower priority. Accordingly, some systems implement significant amounts of logic to enable certain data transactions to pass ahead of other transactions.
Furthermore, some architectures implement split paths, where control portions of a transaction pass through a control path, while data portions of the same transaction pass through a data path. Again, significant logic is needed to maintain synchronization between such paths. Such synchronization is especially needed where the separate paths traverse different clock crossing domains. For example, both control and data paths may cross the same clock crossing, but the service rate of each is dependent on various other conditions, causing control and data paths to lose synchronization. Other implementations incorporate a separate path for data transactions of a higher priority, e.g., so-called snoop transactions. Implementation of significant logic or separate paths for given transactions can significantly affect die area consumed and furthermore contribute to additional power consumption.